Interface and Packet Levels
Interface Level
There are two levels of МИПИ communication which are separated into the interface level and packet level. Low level communication is done on the interface level. The interface level is used to indicate the display’s power and speed settings. It supports modes such as low power, ultra-low power, and high speed. These modes define how the system transitions between sending commands and image data.

The interface level is comprised of different states that drive the data differentially for both high speed mode and low power mode. The switching between these states is managed by driving positive and negative lanes according to defined state codes. The interface level is determined by the application and the capabilities of the host processor.
Packet Level
Packet level communication is used when sending image data to the display in short (4 bytes) or long (6 to 65,541 byte) packets. This layer handles higher-level operations such as transmitting commands, image pixels, and error checking.
Packet Level: Short and Long Packets
The packets are sent in a specific sequence to indicate packet size and error correction codes. Short packets can be sent for commands that do not require data. These are typically used for register control. Longer packets can be used to send commands with multiple bytes of data and image data.
The first byte is the data identifier byte that includes two bits for the virtual channel identifier. This allows up to four peripherals to be controlled via a single MIPI DSI bus. The word count for the long data will indicate how many bytes of data will follow.
Packet Level: Error Correction
The check sum and error correction bytes are specified by the controller for specific functions. These mechanisms ensure reliable transmission over high-speed differential lanes, which is critical in real-time applications like video streaming.
Video and Command Modes
Command Mode
Command mode can be used for displays that have access to frame buffer memory to display images. This mode allows writing directly into display registers using short or long packets. Command mode is what is typically seen with interfaces such as SPI, 8080/6800 parallel MCU, and I2C display controllers.
This mode offers flexibility in low-power operations since it does not require continuous pixel streaming. It suits displays with onboard memory where images can be stored temporarily.
Video Mode
Video mode is when data is sent as a real time pixel stream. This mode relies on the host processor to provide a constant stream of image data that is continuously refreshed. Since no framebuffer exists in such displays, all pixel information must be streamed live.
Video Mode: Packet Structure of Pixel Data RGB-565
Packet level communication in video mode is sent as a constant stream of pixels in a specific sequence. Sync events define active areas similar to RGB interfaces. The sync events specify the start and end of a sync, similar to the RGB interface, to represent the active area of pixel data.
The sync events are sent in short packets which indicate the location and porch lengths. This structure enables precise control over timing without switching between low power and high-speed modes during each frame.
Video Mode: Burst Mode vs Non-Burst Mode
In burst mode, the pixel data is compressed to reserve time for the interface level to return to low power. Non-burst modes rely on sync pulses or events. A sync pulse non-burst mode will require the definition of display pulse widths.
Burst mode helps optimize power consumption while maintaining high-speed transmission. Non-burst modes offer more flexibility in timing but may consume more power due to continuous signaling.

Considerations
Video Mode
Operating the display in video mode requires the packets to be sent in a constant stream using the high-speed interface level. While this ensures real-time rendering, it also increases system power draw significantly. The host processor will have to be able to communicate at the high-speed data transmission rate and as a result require more power to operate in the high-speed mode.
External Memory
External memory can be used to store the frame buffer remotely from the display. However, it introduces challenges like timing constraints and additional energy usage. The frame buffer must be continually refreshed to avoid flickering and loss of image.
Cost Efficiency
Displays that do not contain an internal framebuffer memory location are often less expensive. This cost-saving shifts responsibilities such as memory management or synchronization onto system controllers. There are two options available when internal RAM is not provided by the display. The host processor can provide display memory if there is enough to support the high-level graphics. The other option is to use the video mode where the image data is streamed and not stored.
Часто задаваемые вопросы
Q1: What makes MIPI DSI superior for embedded systems?
MIPI DSI displays have the advantage of high-level graphics at a reduced complexity of signal routing, PCB design, and hardware costs.
Q2: Can MIPI DSI operate at low power?
The MIPI DSI interface can operate at very low power to preserve battery life.
Q3: How many peripherals can MIPI DSI control?
The MIPI DSI can command up to four peripherals using this virtual channel ID.
Q4: What happens if my display has no internal RAM?
You must use video mode or allocate external memory capable of supporting continuous refresh rates.
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Блог и новости
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TN против IPS2024-7-9
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TN против IPS2024-7-9